1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Description of Related Art
In order to enhance the performance of semiconductor LSI devices, traditionally, the design scale is decreased to 0.7 times that of the previous-generation devices based on the Moore's scaling law, to thereby attempt improvement regarding the circuit processing speed, the power consumption, and so on. However, for LSI devices of the 45-nm-generation and the subsequent generations, it is becoming impossible to achieve enhanced performance through mere size shrinking, due to the influence of the abrupt deterioration of the short-channel characteristic of MOSFETs, and so on. To address this problem, as a technique to achieve enhanced performance, a technique of applying strain to a gate to thereby enhance the current of the transistor is being actively researched and developed. As one of methods for this technique, there has been developed a dual stress liner (DSL) technique in which stress is applied to a gate from a contact etch stop layer (CESL) film and the stress value is varied for each of an NMOS transistor region and a PMOS transistor region to thereby allow each of the transistors to achieve the preferred performance (refer to e.g. H. -S. Yang et al., “Dual Stress Liner for High Performance sub-45 nm Gate Length SOI CMOS Manufacturing” IEDM Tech. Dig., p. 1075, 2004).
In many cases, ion implantation of arsenic (As) is performed for the deep source and drain of the NMOS field effect transistor (hereinafter, referred to as NFET), and the same ion implantation is performed also for an N-type substrate region that is formed simultaneously. However, if ion implantation of arsenic (As) is performed and a nickel silicide layer is formed, an abnormal oxide film will be formed on this nickel silicide layer (refer to e.g. Jung-Gn Yun et al., “Abnormal Oxidation of Formed on Arsenic-Doped Substrate” Electrochemical and Solid-State Letters, 7 (4) G83-G85 (2004)), and water and so on will be absorbed by this abnormal film. This will significantly deteriorate the adhesion between the nickel silicide layer and a silicon nitride film as the CESL film. In particular, the following problem will occur if, as shown in FIG. 18, a dense film like a silicon nitride film 241 having compressive stress is applied. Specifically, water will be hardly discharged from an abnormal oxide film (not shown) on the surface of a nickel silicide layer 229 of the case in which ion implantation of arsenic (As) is performed, and thus separation at the interface between the nickel silicide 229 and the silicon nitride film 241 will occur. This problem applies to an N-type substrate region 214 of the case in which a dual stress liner film is applied.
Another problem will also occur if, as shown in FIG. 19A, a compressive silicon nitride film is applied in order to enhance the mobility of a P-type field effect transistor 202 (hereinafter, referred to as PFET). Specifically, compressive stress, which is unfavorable for the PFET, will be applied along the direction of the gate width of a gate electrode 222 (W direction). Thus, although stress is applied along the direction of the gate length of the gate electrode 222 (L direction) by applying the compressive film, the effect of this stress application cannot be brought out to the full. Ideally, it is desired that, as shown in FIG. 19B, tensile stress be applied along the direction of the gate width of the gate electrode 222 (W direction) and compressive stress be applied along the direction of the gate length of the gate electrode 222 (L direction).
Consequently, the problem that should be solved is that, if a dense film such as a compressive film is applied as a silicon nitride film, water absorbed by an abnormal oxide film formed on a nickel silicide layer is hardly discharged and thus separation occurs at the interface between the nickel silicide layer and the silicon nitride film.